? semiconductor components industries, llc, 2005 november, 2005 ? rev. 3 1 publication order number: nb2309a/d nb2309a 3.3 v zero delay clock buffer the nb2309a is a versatile, 3.3 v zero delay buffer designed to distribute high ? speed clocks. it accepts one reference input and drives out nine low ? skew clocks. it is available in a 16 pin package. the ? 1h version of the nb2309a operates at up to 133 mhz, and has higher drive than the ? 1 devices. all parts have on ? chip pll?s that lock to an input clock on the ref pin. the pll feedback is on ? chip and is obtained from the clkout pad. the nb2309a has two banks of four outputs each, which can be controlled by the select inputs as shown in the select input decoding table. if all the output clocks are not required, bank b can be three ? stated. the select inputs also allow the input clock to be directly applied to the outputs for chip and system testing purposes. multiple nb2309a devices can accept the same input clock and distribute it. in this case the skew between the outputs of the two devices is guaranteed to be less than 700 ps. all outputs have less than 200 ps of cycle ? to ? cycle jitter. the input and output propagation delay is guaranteed to be less than 350 ps, and the output to output skew is guaranteed to be less than 250 ps. the nb2309a is available in two dif ferent configurations, as shown in the ordering information table. the nb2309a1 is the base part. the nb2309ax1h* is the high drive version of the ? 1 and its rise and fall times are much faster than ? 1 part. features ? 15 mhz to 133 mhz operating range, compatible with cpu and pci bus frequencies ? zero input ? output propagation delay ? multiple low ? skew outputs ? output ? output skew less than 250 ps ? device ? device skew less than 700 ps ? one input drives 9 outputs, grouped as 4 + 4 + 1 ? less than 200 ps cycle ? to ? cycle jitter is compatible with pentium based systems ? test mode to bypass pll ? available in 16 pin, 150 mil soic and 4.4 mm tssop ? 3.3 v operation, advanced 0.35 cmos technology ? pb ? free packages are available** *x = c for commercial; i for industrial. **for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. marking diagrams* xxxx = device code a = assembly location wl, l = wafer lot y = year w, ww = work week g or = pb ? free package *for additional marking information, refer to application note and8002/d. see detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. ordering information http://onsemi.com tssop ? 16 dt suffix case 948f soic ? 16 d suffix case 751b 1 16 1 16 1 16 1 16 xxxx xxxx alyw xxxxxxxxg awlyww
nb2309a http://onsemi.com 2 clkout clka1 clka2 clka3 clka4 pll mux clkb1 clkb2 clkb3 clkb4 select input decoding figure 1. block diagram ref s2 s1 table 1. select input decoding s2 s1 clock a1 ? a4 clock b1 ? b4 clkout (note 1) output source pll shutdown 0 0 three ? state three ? state driven pll n 0 1 driven three ? state driven pll n 1 0 driven driven driven reference y 1 1 driven driven driven pll n 1. this output is driven and has an internal feedback for the pll. the load on this output can be adjusted to change the skew be tween the reference and the output.
nb2309a http://onsemi.com 3 figure 2. pin configuration v dd 1 2 3 4 16 15 14 13 ref clka1 clka2 gnd clkout clka4 clka3 nb2309a v dd 5 6 7 8 12 11 10 9 clkb1 clkb2 s2 clkb4 clkb3 s1 gnd table 2. pin description pin # pin name description 1 ref (note 2) input reference frequency, 5 v tolerant input. 2 clka1 (note 3) buffered clock output, bank a. 3 clka2 (note 3) buffered clock output, bank a. 4 v dd 3.3 v supply. 5 gnd ground. 6 clkb1 (note 3) buffered clock output, bank b. 7 clkb2 (note 3) buffered clock output, bank b. 8 s2 (note 4) select input, bit 2. 9 s1 (note 4) select input, bit 1. 10 clkb3 (note 3) buffered clock output, bank b. 11 clkb4 (note 3) buffered clock output, bank b. 12 gnd ground. 13 v dd 3.3 v supply. 14 clka3 (note 3) buffered clock output, bank a. 15 clka4 (note 3) buffered clock output, bank a. 16 clkout (note 3) buffered output, internal feedback on this pin. 2. weak pulldown. 3. weak pulldown on all outputs. 4. weak pullup on these inputs.
nb2309a http://onsemi.com 4 table 3. maximum ratings parameter min max unit supply voltage to ground potential ? 0.5 +7.0 v dc input voltage (except ref) ? 0.5 v dd + 0.5 v dc input voltage (ref) ? 0.5 7 v storage temperature ? 65 +150 c maximum soldering temperature (10 sec) 260 c junction temperature 150 c static discharge voltage (per mil ? std ? 883, method 3015) >2000 v maximum ratings are those values beyond which device damage can occur. maximum ratings applied to the device are individual str ess limit values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional operation i s not implied, damage may occur and reliability may be affected. table 4. operating conditions for commercial and industrial temperature devices parameter description min max unit v dd supply voltage 3.0 3.6 v t a operating temperature (ambient temperature) commercial industrial 0 ? 40 70 85 c c l load capacitance, below 100 mhz 30 pf c l load capacitance, from 100 mhz to 133 mhz 10 pf c in input capacitance 7 pf table 5. electrical characteristics for commercial and industrial temperature devices parameter description test conditions min max unit v il input low voltage (note 5) 0.8 v v ih input high voltage (note 5) 2.0 v i il input low current v in = 0 v 50.0 a i ih input high current v in = v dd 100.0 a v ol output low voltage i ol = 8 ma ( ? 1) i ol = 12 ma ( ? 1h) 0.4 v v oh output high voltage i oh = ? 8 ma ( ? 1) i oh = ? 12 ma ( ? 1h) 2.4 v i dd supply current (commercial temp) unloaded outputs at 66.67 mhz, select inputs at v dd 34 ma i dd supply current (industrial temp) unloaded outputs at 100 mhz 66.67 mhz 33 mhz select inputs at v dd or gnd, at room temp 50 34 19 ma 5. ref input has a threshold voltage of v dd /2.
nb2309a http://onsemi.com 5 table 6. switching characteristics (commercial and industrial) (note 6) parameter description test conditions min typ max unit 1/t 1 output frequency 30 pf load 10 pf load 15 15 100 133.33 mhz 1/t 1 duty cycle = (t 2 / t 1 ) * 100 ( ? 1, ? 1h) ( ? 1h) measured at 1.4 v, f out = 66.67 mhz < 50 mhz 40 45 50 50 60 55 % t 3 output rise time ( ? 1, ? 1h) ( ? 1h) measured between 0.8 v and 2.0 v 2.5 1.5 ns t 4 output fall time measured between 2.0 v and 0.8 v 1.5 ns t 5 output ? to ? output skew all outputs equally loaded 250 ps t 6 delay, ref rising edge to clkout rising edge measured at v dd /2 0 350 ps t 7 device ? to ? device skew measured at v dd /2 on the clkout pins of the device 0 700 ps t 8 output slew rate measured between 0.8 v and 2.0 v using test circuit #2 1 v/ns t j cycle ? to ? cycle jitter measured at 66.67 mhz, loaded outputs 200 ps t lock pll lock time stable power supply, valid clock presented on ref pin 1.0 ms tr in ref input rise time measured between 0.8 v to 2.0 v 1.0 ns tf in ref input rise fall time measured between 2.0 v to 0.8 v 1.0 ns 6. all parameters specified with loaded outputs and apply to both pll ? mode and pll ? bypass mode.
nb2309a http://onsemi.com 6 zero delay and skew control all outputs should be uniformly loaded to achieve zero delay between input and output. since the clkout pin is the internal feedback to the pll, its relative loading can adjust the input ? output delay. for applications requiring zero input ? output delay, all outputs, including clkout, must be equally loaded. even if clkout is not used, it must have a capacitive load equal to that on other outputs, for obtaining zero ? input ? output delay. switching waveforms figure 3. duty cycle timing 1.4 v 1.4 v 1.4 v t 1 t 2 figure 4. all outputs rise/fall time t 3 output 2.0 v 0.8 v t 4 2.0 v 0.8 v 3.3 v 0 v 1.4 v 1.4 v t 5 figure 5. output ? output skew output output t 6 input output figure 6. input ? output propagation delay v dd 2 v dd 2 figure 7. device ? device skew t 7 clkout, device 1 v dd 2 v dd 2 clkout, device 2
nb2309a http://onsemi.com 7 test circuits v dd v dd c load gnd gnd outputs figure 8. test circuit #1 10 pf 0.1 f 0.1 f v dd v dd gnd gnd outputs 0.1 f 0.1 f 1 k 1 k figure 9. test circuit #2 for parameter t 8 (output slew rate) on ? 1h devices v dd clkout
nb2309a http://onsemi.com 8 ordering information device marking operating range package shipping ? availability nb2309ac1d 2309ac1 commercial soic ? 16 48 units / rail now nb2309ac1dg 2309ac1g commercial soic ? 16 (pb ? free) 48 units / rail now nb2309ac1dr2 2309ac1 commercial soic ? 16 2500 tape & reel now nb2309ac1dr2g 2309ac1g commercial soic ? 16 (pb ? free) 2500 tape & reel now nb2309ai1d 2309ai1 industrial soic ? 16 48 units / rail now nb2309ai1dg 2309ai1g industrial soic ? 16 (pb ? free) 48 units / rail now nb2309ai1dr2 2309ai1 industrial soic ? 16 2500 tape & reel now nb2309ai1dr2g 2309ai1g industrial soic ? 16 (pb ? free) 2500 tape & reel now nb2309ac1hd 2309ac1h commercial soic ? 16 48 units / rail now nb2309ac1hdg 2309ac1hg commercial soic ? 16 (pb ? free) 48 units / rail now nb2309ac1hdr2 2309ac1h commercial soic ? 16 2500 tape & reel now nb2309ac1hdr2g 2309ac1hg commercial soic ? 16 (pb ? free) 2500 tape & reel now nb2309ai1hd 2309ai1h industrial soic ? 16 48 units / rail now nb2309ai1hdg 2309ai1hg industrial soic ? 16 (pb ? free) 48 units / rail now nb2309ai1hdr2 2309ai1h industrial soic ? 16 2500 tape & reel now nb2309ai1hdr2g 2309ai1hg industrial soic ? 16 (pb ? free) 2500 tape & reel now nb2309ac1dt 2309ac1 commercial tssop ? 16 96 units / rail now nb2309ac1dtg 2309ac1 commercial tssop ? 16 (pb ? free) 96 units / rail now nb2309ac1dtr2 2309ac1 commercial tssop ? 16 2500 tape & reel now nb2309ac1dtr2g 2309ac1 commercial tssop ? 16 (pb ? free) 2500 tape & reel now nb2309ai1dt 2309ai1 industrial tssop ? 16 96 units / rail now nb2309ai1dtg 2309ai1 industrial tssop ? 16 (pb ? free) 96 units / rail now nb2309ai1dtr2 2309ai1 industrial tssop ? 16 2500 tape & reel now nb2309ai1dtr2g 2309ai1 industrial tssop ? 16 (pb ? free) 2500 tape & reel now nb2309ac1hdt 2309ac1h commercial tssop ? 16 96 units / rail now nb2309ac1hdtg 2309ac1h commercial tssop ? 16 (pb ? free) 96 units / rail now nb2309ac1hdtr2 2309ac1h commercial tssop ? 16 2500 tape & reel now nb2309ac1hdtr2g 2309ac1h commercial tssop ? 16 (pb ? free) 2500 tape & reel now nb2309ai1hdt 2309ai1h industrial tssop ? 16 96 units / rail now nb2309ai1hdtg 2309ai1h industrial tssop ? 16 (pb ? free) 96 units / rail now NB2309AI1HDTR2 2309ai1h industrial tssop ? 16 2500 tape & reel now NB2309AI1HDTR2g 2309ai1h industrial tssop ? 16 (pb ? free) 2500 tape & reel now ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
nb2309a http://onsemi.com 9 package dimensions tssop ? 16 case 948f ? 01 issue a ??? ??? dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c ??? 1.20 ??? 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.18 0.28 0.007 0.011 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane ?w?. section n ? n seating plane ident. pin 1 1 8 16 9 detail e j j1 b c d a k k1 h g ? u ? s u 0.15 (0.006) t s u 0.15 (0.006) t s u m 0.10 (0.004) v s t 0.10 (0.004) ? t ? ? v ? ? w ? 0.25 (0.010) 16x ref k n n
nb2309a http://onsemi.com 10 package dimensions notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p ? b ? ? a ? m 0.25 (0.010) b s ? t ? d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019 soic ? 16 case 751b ? 05 issue j on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2 ? 9 ? 1 kamimeguro, meguro ? ku, tokyo, japan 153 ? 0051 phone : 81 ? 3 ? 5773 ? 3850 nb2309a/d pentium is a registered trademark of intel corporation. licensed under us patent nos 5,488,627, 6,646,463 and 5,631,920. literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082 ? 1312 usa phone : 480 ? 829 ? 7710 or 800 ? 344 ? 3860 toll free usa/canada fax : 480 ? 829 ? 7709 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.
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